Arista 7130 Applications

Arista 7130 Applications - FPGA-based network applications

Arista offers several powerful network applications to simplify and transform network infrastructure. These applications are designed for use cases including ultra-low latency exchange trading, network visibility and providing vendor or broker based shared services. These network applications are supported on the Arista’s 7130L and LB devices.

The 7130 applications provided by Arista enable a complete lifecycle of packet replication, multiplexing, filtering, time stamping, aggregation, and capture. In addition to these application functions Arista also provides FPGA IP cores to enable low latency communications and multiplexing functionality in your own custom applications.

7130

Arista 7130 Applications

Application Comparison for Arista 7130 Series

Application	Overview	Key Features	Use it for...
MetaWatch	Advanced network monitoring	Tapping Large scale, lossless tap aggregation Multi-port data capture Sub-nanosecond precise time stamping Deep buffering (32 GB)	In-depth network monitoring and visibility Improved network reliability & troubleshooting problems Market data & packet capture Accurate latency measurement & monitoring Regulatory compliance (MiFID II - RTS 25)
MetaMux	Low-latency multiplexing	Data aggregation in 39 nanoseconds Deterministic jitter Packet statistics BGP & PIM support	Ultra-low latency network connectivity for trading Market data fan-out and data aggregation for order entry at nanosecond levels
MultiAccess	Connection sharing with enhanced security	Low-latency multiplexing and security ACL-based configurable filtering Easy to deploy data privacy for connection sharing Simplified footprint for both mux and filtering applications 10/1G Speed Conversion	Secure network connection sharing Providing sponsored access to multiple clients Multi tenant exchange access Low latency interconnect sharing Supporting Colo deployments with multiple concurrent exchange connection
MetaProtect^TM Firewall	Low-latency packet filtering in 135 ns	48 x 10GbE port network appliance for packet filtering in parallel between port-pairs Cut-through filtering via 32 ACLs with up to 510 rules per ACL Architected for ultra-low-latency with packets passing an ACL being forwarded in 135 ns or less Comprehensive logging	Low-latency firewall
ExchangeApp	Inline timestamping enables exchange fairness	Timestamp at the edge of trading venue networks Sub-200ns passthrough latency to apply the timestamp Reliable accuracy and timestamp precision Accurately synchronise timestamps between multiple ExchangeApp devices	Increase exchange fairness Reduce trading venue latency sensitivity Maintain trade order based on edge timestamps Reduce complexity and risk of traditional low latency exchange infrastructures
SwitchApp	Low latency Layer 2 switching	Full-featured 1/10/40G Layer 2 switching, implemented in FPGA Ultra-low latency packet forwarding in 92-130 ns EOS as well as Layer 1 integration Non-blocking bandwidth profiles to provide up to 480 Gbps	Exchange-facing connectivity L2 Multicast pub/sub

Enabling Custom Applications

While FPGA applications can be challenging to develop, the Arista 7130 makes them easy to deploy. Arista provides a built-in application framework allowing developers to wrap applications into simple packages for deployment, streamlining operational processes. Arista development toolkits enable complete and unfettered access to the facilities provided by the in-system FPGAs. The MOSAPI provides monitoring, CLI, API, FPGA image management, and other facilities to allow application developers to concentrate on the core application functionality. These are the same APIs and developer kits used by the Arista engineering team to develop and deploy our applications.

Enyx is a leading developer of ultra-low latency, FPGA-based solutions for a wide range of financial technology applications, including market data distribution, order execution, and network connectivity management.

Enyx Applications for Arista 7130 Series

Application	Compatible with	Overview	Key Features
nxLink - Share Enterprise	Arista 7130E & 7130L Series	Bandwidth management for RF links	Share bandwidth and police user traffic in a fair/deterministic way (Up to 30 user ports) Aggregate multiple radio links into one or manage multiple destinations Ultra Low Latency: 10GbE radio interface (microwave) 530 ns User-to-User latency for 1 Byte payload 1GbE radio interface (millimeter wave) 641 ns User-to-User latency for 1 Byte payload Optimize bandwidth with up to 1.2Gb/s on compatible 1GbE Layer 1 radios Monitor network status with live link latency monitoring and historical data access
nxLink - Share Lite	Arista 7130L Series	Bandwidth management for RF links	Same features/performance as nxLink Share Enterprise Offers entry level option for smaller networks; limited to 12 physical user ports, no virtual user support and one single radio port
nxLink - Share Node	Arista 7130L Series	Low Latency Network Router	Component of the nxLink Share infrastructure 1GbE and 10GbE radio interface compliant
nxLink - Secure	Arista 7130L Series	Packet arbitration for link redundancy	Zero packet loss: Secures an unreliable RF link using a stable backup fiber network Duplicates ingress packets and performs deduplication on the receiving device Maintains TCP connections over RF links and prevents client disconnects Latency: 200 ns user-to-user latency for 64 byte payload Integration with nxLink Share: Monitor packet time spent in input buffers
.Enyx Case Study

The Arista 7130E and L Series devices leverage the latest FPGA technology to enable the development and deployment of cutting-edge network applications. Arista provides a set of mature development kits as well as IPCores to enable firms to build their own applications based on these building blocks.

Arista 7130 - Developer Kits

1. The Arista 7130 FPGA Development Kit (or Arista FDK):

The Arista FDK provides the documentation, libraries and examples which enable developers to build new FPGA applications running on Arista’s 7130 platform. The development environment includes:

Hardware documentation and information (currently supporting the 7130 E, EH, L and LB development standards)
IP Cores
Working example applications, including example build systems*
Support resources to correctly build FPGA applications.

*The examples in the Arista FDK target the MOS operating system, and its MOSAPI SDK. As the 7130 series transitions to EOS, these applications will transition to an enhanced EOS SDK. Please get in touch to discuss your specific SDK feature requirements. EOS application examples will be added in Q4, 2020.

The Arista FDK includes all current Arista IP cores (FPGA libraries). These include:

10G MAC-PHY IP Core: a Ultrascale/Ultrascale+ MACPHY, which is a combined 10GbE/1GbE, low latency design that implements the MAC, PCS & PMA reconciliation layers as four independent channels grouped per the Xilinx transceiver “Quad”.
Mux IP Core: a Ultrascale+ 10GbE Mux, which is Arista’s Low Latency MetaMux Application in an IP Core, with the addition of fabric AXI4 Stream interfaces to inject packets directly from the custom logic.
TS IP Core: A clock synchronisation and timestamping core which combines both hardware and software components to synchronise the hardware within 7130 to a PPS, PTP or NTP time source, and use that synchronised clock to measure timestamps.

2. The Arista Switch Development Kit for Vitis™

Vitis is a powerful tool, designed by Xilinx, to better enable FPGA development. Vitis is designed to make it simpler to build FPGA applications using higher-level languages, reusable blocks, and a statically configured Vitis Target Platform in the FPGA. Arista provides support for Vitis development, via these Vitis Target Platforms which run on the LB development standard and support the many Ethernet interfaces provided by the 7130LB devices. The Switch’s internal CPU connects via PCIE to the FPGA, and supports XRT, giving a similar development experience to that of a server with an add-in PCIE card.

The Arista Switch Development Kit for Vitis provides:

MOS support for running Vitis target platforms. Arista’s MOS includes Xilinx’s XRT and its drivers
A Vitis target platform for the FPGA in the Arista 7130 LB devices;
An Arista app for managing the shells installed on a switch;
An Arista 10GbE Ethernet kernel, including an example application using the Ethernet kernel;
Example Vitis projects, including Xilinx’s Market Maker example, and a software layer used to integrate this into the switch’s operating system.

Note: The Arista FPGA Development Kit for Vitis supports the MOS Operating System. Along with the Arista FDK, support for Arista’s EOS will be added in Q4 2020.

Arista 7130 Applications - IP Cores

Arista develops FPGA applications based on a mature base of network logic IP and licenses the IP as IP Cores for use on the Arista 7130 platform. These are supported, proven building blocks that reduce the time to implement your applications.

Core	Overview	Use it for...
10G MAC-PHY IP Core	An IP core for interfacing 10 gigabit Ethernet with low latency. Implements a low latency Ethernet MAC and Physical layer (10GBASE-R) Connects directly to FPGA top level serial transceiver pins and provides separate AXI4 interfaces for RX and TX user data Supports Xilinx Virtex® 7, Xilinx Kintex® UltraScale™, and Virtex® UltraScale+™ FPGA's.	Accelerating your own applications access to the 10G network
Mux IP Core	Implements the same functionality as the Arista MetaMux application. Allows for customizable radix and number of multiplexing cores e.g. one 4:1, plus a 13:1, plus a 14:1, etc	Sharing the FPGA between the mux functionality and your own application Building a multiplexing app with different configurations than the standard MetaMux application.
MMP IP Core	Provides a bus that leverages parallel I/O between FPGA’s on the 7130 triple FPGA platforms 8 ns intra FPGA latency Provides a low latency clock domain crossing FIFO Supports four MMP links connecting each Leaf FPGA to the Central FPGA and two MMP links connecting the two Leaf FPGAs together	The lowest latency , parallel communications bus for your multi FPGA applications The fastest way to involve two FPGAs in a trading decision such as “splitting risk logic from trading logic”.
Timestamp IP Core (TS IPCore)	Provides a timestamping and synchronisation engine, implemented as a combination of an encrypted RTL core, with a python based synchronisation daemon. When instantiated in a design, the RTL core and software combination allows the system’s OCXO to be synchronised to a PPS, PTP or NTP source. Multiple timestamper units can be instantiated to sample asynchronous strobes, providing nanosecond-precise timestamps within the RTL. The TS IP Core solution has the following specifications: 1ns timestamp resolution with a +/- 2ns precision Configurable triggering	Integrate accurate timestamping into your own apps, without having to build and calibrate synchronisation infrastructure. Utilise precisely synchronised frequencies for Video or other synchronous systems.

Partner Ecosystem

Several tried & tested integrations exist via our technology partners. We enable our partners to deliver value and differentiation in a highly competitive marketplace. Joint innovation with our partners has proven to generate powerful complementary solutions that run on the 7130 platform and offer clients additional capabilities: optimized analytics, data capture solutions, and more.

Arista 7130 Applications

Arista 7130 Applications - FPGA-based network applications

Arista 7130 Applications

Application Comparison for Arista 7130 Series

Enabling Custom Applications

Enyx Applications for Arista 7130 Series

Arista 7130 - Developer Kits

Arista 7130 Applications - IP Cores

Partner Ecosystem

Quick Looks

Product Overview

White Papers

Product Briefs

Solution Briefs

Case Study

Video