Arista 7130 Applications - FPGA-based network applications
Arista offers several powerful network applications to simplify and transform network infrastructure. These applications are designed for use cases including ultra-low latency exchange trading, network visibility and providing vendor or broker based shared services. These network applications are supported on the Arista’s 7130L and LB devices.
The 7130 applications provided by Arista enable a complete lifecycle of packet replication, multiplexing, filtering, time stamping, aggregation, and capture. In addition to these application functions Arista also provides FPGA IP cores to enable low latency communications and multiplexing functionality in your own custom applications.
Arista 7130 Applications
Application Comparison for Arista 7130 Series
Use it for...
||Advanced network monitoring||
||Connection sharing with enhanced security||
||Low-latency packet filtering in 135 ns||
||Inline timestamping enables exchange fairness||
||Low latency Layer 2 switching||
Enabling Custom Applications
While FPGA applications can be challenging to develop, the Arista 7130 makes them easy to deploy. Arista provides a built-in application framework allowing developers to wrap applications into simple packages for deployment, streamlining operational processes. Arista development toolkits enable complete and unfettered access to the facilities provided by the in-system FPGAs. The MOSAPI provides monitoring, CLI, API, FPGA image management, and other facilities to allow application developers to concentrate on the core application functionality. These are the same APIs and developer kits used by the Arista engineering team to develop and deploy our applications.
Enyx is a leading developer of ultra-low latency, FPGA-based solutions for a wide range of financial technology applications, including market data distribution, order execution, and network connectivity management.
Enyx Applications for Arista 7130 Series
|Application||Compatible with||Overview||Key Features|
|nxLink - Share Enterprise||Arista 7130E
& 7130L Series
|Bandwidth management for RF links||
|nxLink - Share Lite||Arista 7130L Series||Bandwidth management for RF links||
|nxLink - Share Node||Arista 7130L Series||Low Latency Network Router||
|nxLink - Secure||Arista 7130L Series||Packet arbitration for link redundancy||
|.Enyx Case Study|
The Arista 7130E and L Series devices leverage the latest FPGA technology to enable the development and deployment of cutting-edge network applications. Arista provides a set of mature development kits as well as IPCores to enable firms to build their own applications based on these building blocks.
Arista 7130 - Developer Kits
1. The Arista 7130 FPGA Development Kit (or Arista FDK):
The Arista FDK provides the documentation, libraries and examples which enable developers to build new FPGA applications running on Arista’s 7130 platform. The development environment includes:
- Hardware documentation and information (currently supporting the 7130 E, EH, L and LB development standards)
- IP Cores
- Working example applications, including example build systems*
- Support resources to correctly build FPGA applications.
*The examples in the Arista FDK target the MOS operating system, and its MOSAPI SDK. As the 7130 series transitions to EOS, these applications will transition to an enhanced EOS SDK. Please get in touch to discuss your specific SDK feature requirements. EOS application examples will be added in Q4, 2020.
The Arista FDK includes all current Arista IP cores (FPGA libraries). These include:
- 10G MAC-PHY IP Core: a Ultrascale/Ultrascale+ MACPHY, which is a combined 10GbE/1GbE, low latency design that implements the MAC, PCS & PMA reconciliation layers as four independent channels grouped per the Xilinx transceiver “Quad”.
- Mux IP Core: a Ultrascale+ 10GbE Mux, which is Arista’s Low Latency MetaMux Application in an IP Core, with the addition of fabric AXI4 Stream interfaces to inject packets directly from the custom logic.
- TS IP Core: A clock synchronisation and timestamping core which combines both hardware and software components to synchronise the hardware within 7130 to a PPS, PTP or NTP time source, and use that synchronised clock to measure timestamps.
2. The Arista Switch Development Kit for Vitis™
Vitis is a powerful tool, designed by Xilinx, to better enable FPGA development. Vitis is designed to make it simpler to build FPGA applications using higher-level languages, reusable blocks, and a statically configured Vitis Target Platform in the FPGA. Arista provides support for Vitis development, via these Vitis Target Platforms which run on the LB development standard and support the many Ethernet interfaces provided by the 7130LB devices. The Switch’s internal CPU connects via PCIE to the FPGA, and supports XRT, giving a similar development experience to that of a server with an add-in PCIE card.
The Arista Switch Development Kit for Vitis provides:
- MOS support for running Vitis target platforms. Arista’s MOS includes Xilinx’s XRT and its drivers
- A Vitis target platform for the FPGA in the Arista 7130 LB devices;
- An Arista app for managing the shells installed on a switch;
- An Arista 10GbE Ethernet kernel, including an example application using the Ethernet kernel;
- Example Vitis projects, including Xilinx’s Market Maker example, and a software layer used to integrate this into the switch’s operating system.
Note: The Arista FPGA Development Kit for Vitis supports the MOS Operating System. Along with the Arista FDK, support for Arista’s EOS will be added in Q4 2020.
Arista 7130 Applications - IP Cores
Arista develops FPGA applications based on a mature base of network logic IP and licenses the IP as IP Cores for use on the Arista 7130 platform. These are supported, proven building blocks that reduce the time to implement your applications.
Use it for...
|10G MAC-PHY IP Core||
An IP core for interfacing 10 gigabit Ethernet with low latency.
|Mux IP Core||
|MMP IP Core||
Provides a bus that leverages parallel I/O between FPGA’s on the 7130 triple FPGA platforms
Timestamp IP Core (TS IPCore)
Provides a timestamping and synchronisation engine, implemented as a combination of an encrypted RTL core, with a python based synchronisation daemon.
When instantiated in a design, the RTL core and software combination allows the system’s OCXO to be synchronised to a PPS, PTP or NTP source.
Multiple timestamper units can be instantiated to sample asynchronous strobes, providing nanosecond-precise timestamps within the RTL.
The TS IP Core solution has the following specifications:
Several tried & tested integrations exist via our technology partners. We enable our partners to deliver value and differentiation in a highly competitive marketplace. Joint innovation with our partners has proven to generate powerful complementary solutions that run on the 7130 platform and offer clients additional capabilities: optimized analytics, data capture solutions, and more.
- .5 Ways to Optimise exchange connectivity latency
- .5 Things to Consider When Choosing an FPGA platform
- .Measuring the Absolute Accuracy of 10GbE Packet Timestamping
- .Four key trends in the networked use of FPGAs
- .STAC-TS™ BENCHMARKS
Accuracy of network timestamping and burst capacity of capture
- .MetaWatch Product Brief
- .MetaMux Product Brief
- .MetaProtect Product Brief
- .ExchangeApp Product Brief
- .MultiAccess Product Brief
- .SwitchApp Product Brief
- .Developer Product Brief
- .Case Study: Electronic trading firm gains ultra-low latency exchange connectivity with Arista
- .Case Study: Deutsche Börse Group monitors every trade with Arista