Tag :: L1

Agile ports allow users to connect 40G interfaces on 7130 products utilizing multiple SFP ports per 40G capable interface. This enables 40G capable applications, such as MetaConnect and MetaWatch, to operate at that speed.

Arista’s DCS-7130B series of switches are network devices designed for ultra low-latency applications along with a suite of networking features.

This feature adds support for the front panel Ethernet (Et) interface counters on the platforms listed below and enables the Et interfaces to dynamically adopt the counter values (packet and error)1 of interfaces (Switch, App interfaces etc.) related to the currently running FPGA application, based on user or default configuration. All Arista FPGA applications are supported. Both the receive and transmit packet counters can be independently configured for each interface, as desired. Counters are supported for interfaces of any speed including agile ports.

In general, EOS always configures the PHYs to have the correct polarity to match that of the standard, such that if a standard compliant transceiver is plugged in and the peer is standard compliant everything will work.

For an octal port such as a QSFPDD or OSFP, this feature renumbers the ports on a system to have 4 configurable

The on boot link override feature adds support for keeping interfaces down at switch boot until the correct interface state can be determined by feature agents. Keeping the interfaces down through device boot will protect against transient traffic loss by preventing downstream peers from detecting a transient interface up and sending traffic to the device. 

This document covers the usage of port-breakout CLI to break a port evenly into multiple interfaces. In the context of this document, a port is a logical entity that holds a list of interfaces, in most cases this is equivalent to the front panel transceiver cage.

Interfaces will transition into an error disabled state due to reasons like excessive link flaps or speed mismatch. A