Arista 7130LBR Series Composable Switches

Comprising a feature rich, high bandwidth, deep buffer 7280R3 class switch chip with two large scale VU9P-3 FPGAs, a large Layer 1+ crosspoint, precision clocks and eight-core x86 control plane, the 7130LBR builds on the foundations of the 7130LB family to create a complete single device solution.

With up to 96 front panel connections using a combination of SFP+ and high density, eight-lane QSFP-DD connectors, a single 7130LBR can replace multiple individual layer 1, FPGA and L2/3 devices and dramatically reduce cable count and complexity.

Co-location of layer 1, FPGA, switching and x86 allows applications to take advantage of the individual strengths of each processing element to maximize the efficiency of programmable resources and avoid the latency penalty of offloading traffic to an external device.

The two Xilinx VU9P-3 FPGAs support the existing Arista LB development standard and are optimized for Arista’s network applications. Two applications can be run in parallel and the FPGAs can run 3rd party partner applications or in-house developed performance critical apps.

On top of the market-leading FPGA functionality, the devices combine a multitude of Layer 1-3 network functionality including:

  • Signal regeneration
  • Port mirroring
  • Dynamic patching/link management
  • Ad-hoc tapping without rewiring
  • Layer 1+ statistics on every link
  • Media conversion
  • Telemetry
  • R Series switching and routing stack
  • DANZ tap aggregation


Robust Switches with Comprehensive Feature Sets

Feature Description
Composable Platform Configure dual FPGAs and a full-featured switch across an any-to-any low latency crosspoint for a variety of applications and use cases.
High Density Reduce rack space and consolidate many devices in one with 96 x 10G lanes in only 1RU.
Simplified Stack Centralize configuration and management through one resilient EOS control-plane, featuring multiple API options and streaming telemetry.
Integrated with existing FPGA tools Accelerate custom development with sample projects for Xilinx Vivado and support for the Xilinx Vitis shell.
Layer 1+ functionality Save rack space and reduce complexity by leveraging dynamic patching, tapping, one-to-many replication, telemetry and comprehensive port statistics.
Layer 2/3/4 functionality Route and switch packets with the integrated 7280R3 class switch, or operate in tap aggregation mode with traffic steering and timestamping capabilities.
Feature rich Avoid the need to build features in-house by leveraging Arista’s access control, syslog, SNMP, packet stats, tcpdump, JSON RPC API, time series data, streaming telemetry and more - included as standard within the 7130 Series.
Easy app deployment Streamline operational processes through Arista’s built-in application infrastructure which allows developers to wrap applications into simple packages for deployment.
Enterprise ready Deploy FPGA applications with ease - the FPGA platform integrates with a 64-bit x86 management processor and the EOS Operating system to provide user extensible solutions.
Ultra-low latency Fan-out with virtually no jitter and only 6 ns of latency across 96 x 10G lanes.
7130B Series Devices
Model System Configuration Components FPGA Board Standards SFP+ Ports QSFP-DD (10G NRZ) Ports FPGA Ports Off-Chip RAM RU Switch Chip Ports  PPS In/Out Clock SSD CPU Ports
48S6QD Layer 1 Crosspoint 2 x Xilinx Virtex® UltraScale+™ VU9P-3 FPGA Broadcom Jericho 2C LB  48  96 L1 18 to switch 4x 8 GB DDR4 2400 ECC Per FPGA 1 96 L1 2x9 to FPGAs 2/2  OCXO 120 GB 3

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