Arista 7130 IP Cores

An IP core for interfacing 10 gigabit Ethernet with low latency.

• Implements a low latency Ethernet MAC and Physical layer
• Connects directly to FPGA top level serial transceiver pins and provides separate AXI4 interfaces for RX and TX user data
• Supports Xilinx Virtex^® 7, Xilinx Kintex^® UltraScale™, and Virtex^® UltraScale+™ FPGA's

• Accelerating your own applications access to the 10G network

An IP core for interfacing 25 gigabit Ethernet with low latency.

• Implements a low latency Ethernet MAC and Physical layer
• Connects directly to FPGA top level serial transceiver pins and provides separate AXI4 interfaces for RX and TX user data
• Supports Xilinx Kintex^® UltraScale™, and Virtex^® UltraScale+™ FPGA's

• Accelerating your own applications access to the 25G network

• Implements the same functionality as the Arista MetaMux application
• Allows for customizable radix and number of multiplexing cores e.g. one 4:1, plus a 13:1, plus a 14:1, etc.

• Sharing the FPGA between the mux functionality and your own application
• Building a multiplexing app with different configurations than the standard MetaMux application

Provides a bus that leverages parallel I/O between FPGAs on the 7130 triple FPGA platforms.

• 8ns intra FPGA latency
• Provides a low latency clock domain crossing FIFO
• Supports four MMP links connecting each Leaf FPGA to the Central FPGA and two MMP links connecting the two Leaf FPGAs together

• The lowest latency, parallel communications bus for your multi FPGA applications
• The fastest way to involve two FPGAs in a trading decision such as "splitting risk logic from trading logic"

Provides a timestamping and synchronisation engine, implemented as a combination of an encrypted RTL core, with a python based synchronisation. daemon.

When instantiated in a design, the RTL core and software combination allows the system's OCXO to be synchronised to a PPS, PTP or NTP source.

Multiple timestamper units can be instantiated to sample asynchronous strobes, providing nanosecond-precise timestamps within the RTL.

The TS IP Core solution has the following specifications:

• 1ns timestamp resolution with a +/- 2ns precision
• Configurable triggering

• Integrating accurate timestamping into your own apps, without having to build and calibrate synchronisation infrastructure
• Utilising precisely synchronised frequencies for video or other synchronous systems