Tag :: FEC

The FIB contains mappings between a prefix (identifying a destination network) and its associated Forwarding Equivalence Class (FEC), with the FEC containing one or more resolved Vias defining how traffic should be forwarded towards that destination network.

This feature provides the functionality to bypass error indication to the PCS layer when Forward Error Correction (FEC) is in operation for an interface. Depending on the PHY implementation, there can be one or multiple FEC decoders when an error correction encoding is in use. Upon receiving a codeword, FEC decoders will attempt to test and see if the codeword can be decoded. If there were errors in the codeword

This document describes the Fec Dampening feature. When hardware FEC / ECMP resources usage go above the platform limit, Ale (HW Abstraction layer ) deletes some routes in the anticipation of freeing up some more hardware FEC resources to allow newly created FEC to get programmed. The above logic of deleting/unprogramming the route may lead to unnecessary traffic drop in the following cases of transient FEC resources overflow.

In order for forwarding equivalence classes (FECs) to get programmed in the ASIC, they must have some form of a

A forwarding equivalence class (FEC) entry is the data structure that holds all reachable vias where the packets should be sent to, for certain routes. Before this feature, a FEC could not contain both IPv4 next hop vias and IPv6 next hop vias. This feature starts supporting FECs that have both IPv4 next hop vias and IPv6 next hop vias. In an Equal Cost Multi-Path (ECMP) FEC, some of the vias may have IPv4 next hop and others may have IPv6 next hop.