Tag :: 4.26.2F

Starting with 4.26.2F the platform default traffic class (TC) to network qos will be configurable via a CLI. The

The route reflector, as described in RFC 4456, is a router allowed to advertise (reflect) iBGP learned routes to other

In order for forwarding equivalence classes (FECs) to get programmed in the ASIC, they must have some form of a

Macro Segmentation Service with Layer 3 firewall (MSS FW) enforces all security policies bi directionally by

A router keeps track of the total number of LSAs for each OSPFv3 instance. The LSA Limit feature provides a mechanism to

Line cards, fabric cards, and switch cards now alert the user whenever a card consumes excessive power. There are

This feature extends the existing functionality to set explicit next hop addresses for vpn ipv4 and vpn ipv6 routes.

This feature adds a SNMP CLI knob to allow an interface’s speed, as shown in IF MIB, to reflect its shaped bandwidth.

Starting with 4.26.2F it is possible to assign costs to Shared Risk Link Groups (SRLGs) which will be taken into

This TOI describes details and limitations of Stateful Switchover on Modular chassis with 7500R3, 7800R3, 7800R3A based line cards.

Sub second switchcard failover is a redundancy mode available on systems with two switchcards. One switchcard is the

BGP address aggregation was previously only supported for IPv4 and IPv6 unicast address families. Equivalent BGP

This feature extends the capabilities of Tap Aggregation traffic steering to allow for using interface traffic policies. Initially, interface traffic policies only allowed packet drop, count, qos (set traffic class, set dscp) and log actions.

Timestamping is an important tool for network engineering and performance analysis. The timestamp can be applied to a packet as either an inserted header or replacing the source MAC address of the original packet. Timestamps are recorded on ingress and applied on egress.

Common Management Interface Specification (CMIS) compliant transceivers are configured by selecting an

Current VXLAN decapsulation logic requires the following hits on affected switches listed in the following