Tag :: 7130

Agile ports allow users to connect 40G interfaces on 7130 products utilizing multiple SFP ports per 40G capable interface. This enables 40G capable applications, such as MetaConnect and MetaWatch, to operate at that speed.

Arista’s DCS-7130B series of switches are network devices designed for ultra low-latency applications along with a suite of networking features.

Arista’s DCS-7130LBR series of switches are powerful network devices designed for ultra latency applications along with a wealth of networking features.

This feature adds support for the front panel Ethernet (Et) interface counters on the platforms listed below and enables the Et interfaces to dynamically adopt the counter values (packet and error)1 of interfaces (Switch, App interfaces etc.) related to the currently running FPGA application, based on user or default configuration. All Arista FPGA applications are supported. Both the receive and transmit packet counters can be independently configured for each interface, as desired. Counters are supported for interfaces of any speed including agile ports.

Arista's 7130 Connect Series of Layer 1+ switches are powerful network devices that allow for dynamic connections between various layer 1 components on the system, such as the front panel, FPGA, and ASIC ports. 

4.29.1F adds Latency Analyzer (LANZ) support to the Arista SwitchApp on 7130 series. LANZ monitors SwitchApp internal buffer congestion. When the number of bytes in a buffer is over a high threshold, a congestion start event is created. When the number of bytes in a buffer is below a low threshold, a congestion end event occurs. LANZ on SwitchApp does not report any congestion update as the buffer sizes are too small for it to be meaningful. As SwitchApp comes in different profiles, each profile has a different hardware behavior due to the underlying architectural difference.

This feature adds support for Layer1-only front panel Ethernet ports on 7130 devices (containing a layer1 crosspoint chip) to participate in LLDP. As of 4.33.1F only internal Switch interfaces on ASICs/FPGAs participate in the LLDP protocol. The neighbor also only sees these internal ports from the switch. Customers who really care about/rely on LLDP information of  the front panel Ethernet ports, especially for making cabling changes, would need to translate the internal interface to the appropriate Ethernet port using the show l1 path output.

Arista's 7130 Connect Series of Layer 1+ switches are powerful network devices designed for ultra low latency and offer a wealth of integrated management features and functionalities.

MetaMux is an FPGA-based feature available on Arista’s 7130 platforms. It performs ultra-low latency Ethernet packet multiplexing with or without packet contention queuing. The port to port latency is a function of the selected MetaMux profile, front panel ingress port, front panel egress port, FPGA connector ingress port, and platform being used.

MetaWatch is an FPGA-based feature available for Arista 7130 Series platforms. It provides precise timestamping of packets, aggregation and deep buffering for Ethernet links. Timestamp information and other metadata such as device and port identifiers are appended to the end of the packet as a trailer.

MultiAccess is an FPGA-based feature available on certain Arista 7130 platforms. It performs low-latency Ethernet multiplexing with optional packet contention queuing, storm control, VLAN tunneling, and packet access control. The interface to interface latency is a function of the selected MultiAccess profile, front panel interfaces, MultiAccess interfaces, configuration settings, and platform being used.

SwitchApp is an FPGA-based feature available on Arista’s 713x-Series platforms. It performs ultra low latency Ethernet packet switching. Its packet switching feature set, port count, and port to port latency are a function of the selected SwitchApp profile. Detailed latency measurements are available in the userguide on the Arista Support site.

Arista’s DCS-7130LBR series of switches are capable of supporting SwitchApp, which is an FPGA-based L2/L3 switch. However, as the switch would then contain two switch ASICs (one traditional switch ASIC, and one FPGA-based switch) physically upon loading the SwitchApp application, there are certain limitations and nuances along with its usage. This document intends to explain some of the details.